3-Bus Architecture Allows Dual Operand Fetches in Every The ADSP combines the ADSP family base architecture (three computational units, data. Analog Devices Inc. ADSP Series Digital Signal Processors based controllers have the same bit fixed-point architecture as the C28x DSCs. Memory—The ADSP family uses a modified Harvard architecture in which data Feature. 21msp
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So far, we have described the physical architecture of the DSP processor, explained how DSP can provide some advantages over traditionally analog circuitry, and examined digital filtering, showing how the programmable nature of DSP lends itself to such algorithms. Many of the architectural features of the DSP, such as the ability to perform zero-overhead loops, and to fetch two data values in a single processor cycle, will be useful in implementing this filter.
Reviewing briefly, an FIR filter is an all-zeros filter that is calculated by convolving an input data-point series with filter coefficients.
Its governing equation and direct-form representation are shown in Figure 1. In this structure, each “z —1 ” box represents a single increment of history of the input data in z-transform notation. Each of the successively delayed samples is multiplied by the appropriate coefficient value, h mand the results, added together, generate a single value representing the output corresponding to the nth input sample.
The filter structure suggests the physical elements needed to implement this algorithm by computation using a DSP. For the computation itself, each output sample requires a number of multiply-accumulate operations equal to the length of the filter.
The delay line for input data and the coefficient value list require reserved areas of memory in the DSP for storing data values and coefficients. With Data Memory holding the incoming samples, and Program Memory storing the coefficient values, both a data value and a coefficient value can be fetched in a single cycle for computation. This DSP architecture favors programs that use circular buffering discussed briefly in Part 2 and later in this installment.
The implication is that address pointers need to be initialized only at the beginning of the program, and the circular buffering mechanism ensures that the pointer does not leave the bounds of its assigned memory buffer—a capability used extensively in the FIR filter code for both input delay line and coefficients. Once the elements of the program have been determined, the next step is to develop the DSP source code to implement the algorithm.
Figure 2 shows a typical development cycle. First, the user creates a software description of the hardware system on which the algorithm runs. The system description file includes all available memory in the system and any memory-mapped external peripherals.
Moving from theory into practice, this step—where an algorithmic idea is turned into code that runs on the DSP—is often the most time-consuming step in the process. There are several ways to generate source code. Most effective is combining C for high-level program-control functions and assembly code for the time-critical, math-intensive portions of the system. This phase tests the results of code generation—using a software tool known as a simulator — to check the logical flow of the program and verify that an algorithm is performing as intended.
The simulator is a model of the DSP processor that a provides visibility into all memory locations and processor registers, b allows the user to run the DSP code either continuously or one instruction at a time, and c can simulate external devices feeding data to the processor. Here the code is run on a real DSP, typically in several phases: After all debug is complete, a boot ROM of the final code can be generated; it serves as the final production implementation. To complete the architecture description phase, one needs to know the memory and memory-mapped peripherals that the DSP has available to it.
Programmers store this information in a system-description file so that the development tools software can produce appropriate code for the target system. Available system resources information is recorded in a system description file for use by the ADSP Family development tools.
A system description file has a. The listing declares 16, locations of PM as RAM, starting at address 0, to let both code segments and data values be placed there. Also declared are 16, available locations of data memory as RAM, starting at address 0. Because these processors use a Harvard architecture with two distinct memory spaces, PM address 0 is distinct from DM address 0. To make the system description file available to other software tools, the System Builder utility, BLD21, converts the.
SYS file into an architecture, or.
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After writing the code, the next step is to generate an executable file, i. First one assembles the DSP code. This converts the program file into a format that the other development tools can process. Assembling also checks the code for syntax errors. Next, one links the code to generate the DSP executable, using the available memory that is declared in the architecture file.
The Linker fits all of the code and data from the source code into the memory space; the output is a DSP executable file, which can be downloaded to the EZ-Kit Lite board. Part 2 architectuure this series [Analog Dialoguepage 14, Figure 6] introduced a small assembly code listing for an FIR filter. The core filter-algorithm elements multiply-accumulates, data addressing using circular buffers for both data and coefficients, and reliance on the efficiency of the zero-overhead loop do not change.
The incoming data will be sampled using the on-board AD codec, which has programmable sampling rate, input gain, output archiitecture, input selection, and input mixing.
Its programmable nature makes the system flexible, but it also adds a task of programming to rachitecture it for the DSP system. For this example, a series of control words to the codec—to be defined at the beginning of the program in the first section of the listing—will initialize it for an 8-kHz sampling rate, with moderate gain values on each of the input channels.
Since the AD is programmable, users would ads reuse interface and initialization code segments, changing only the specific register values for different applications. This example will add the specific filter segment to an existing code segment found in the EZ-Kit Lite software.
Each of these memory areas, or buffers, contains three elements, a control or status word, left-channel data, and right-channel data. For each sample period, the DSP will receive from the codec a status word, left channel data, and right channel data.
On every sample period, the DSP must supply to the codec a transmit control word, left channel data, and right channel data. In this application, the control information sent to the codec will not be altered, so the first word in the transmit data buffer will be left as is.
We will assume that the source is a monophonic microphone, using the right channel no concern about left-channel input data. This section of code is accessed when new data is received from the codec ready to be processed. The data arriving from the codec needs to be fed into the filter algorithm via the input delay line, using the circular buffering capability of the ADSP The length of the input delay line is determined by the number of coefficients used for the filter.
Because the data buffer is circular, the oldest data value in the buffer will be wherever the pointer is pointing after the last filter access Figure 4. Likewise the coefficients, always accessed in the same order every time through the filter, are placed wrchitecture a circular buffer in Program Memory.
To operate on the received data, the code section published in the last installment can be used with 281 modifications.
This allows intermediate filter values to grow and shrink as necessary without corrupting data. The code segment being used is generic i. To do this and be ready for the next data pointthe MAC instruction is written in the form of a loop. A counter is set to the number of taps minus one, and the loop mechanism automatically decrements the counter for each loop operation. Setting the loop counter to “taps—1” ensures that the data pointers end up wdsp the correct location after execution is finished and allows the final MAC operation to include rounding.
As the AD is a bit codec, the MAC with rounding provides a statistically unbiased result rounded to the nearest bit value.
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Archietcture final result is written to the codec. For optimal code execution, every instruction cycle should perform a meaningful mathematical calculation. The ADSPxxs accomplish this with multi-function instructions: This capability means adssp on every loop iteration a MAC operation is being performed.
At the same time, the next data value and coefficient are being fetched, and the counter is architectude decremented. All without wasting time maintaining loops. The final source code listing is shown on page The filter algorithm itself is listed under “Interrupt service routines”.
The rest of the code is used for codec and DSP initialization and interrupt service routine definition. Those topics will be explored in future installments of this series. This is accomplished through the pull-down “Loading” menu by selecting “Download user program and Go” Figure 5.
This will download the filter program to the ADSP and start program execution. The goal of this article was to outline the steps from an algorithm description to a DSP executable program that could be run on a architectyre development platform.
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There are many levels of detail associated with each of these topics that this brief article could not do justice to. Further information is available in the references below.
The series will continue to build on this application with additional topics. Part 1 Part 2 Archiyecture 4. Noam Levine joined MathWorks in in technical marketing, focusing on Model-Based Design workflows targeting embedded platforms. Please Select a Region. Please Select a Language.